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FEATURES
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LTC4009 LTC4009-1/LTC4009-2 High Efficiency, Multi-Chemistry Battery Charger DESCRIPTION
The LTC4009 is a constant-current/constant-voltage battery charger controller. It uses a synchronous quasi-constant frequency PWM control architecture that will not generate audible noise with ceramic bulk capacitors. Charge current is set by the combination of external sense, input and programming resistors. With no built-in termination, the LTC4009 family charges a wide range of batteries under external control. The LTC4009 features a fully adjustable output voltage, while the LTC4009-1 and LTC4009-2 can be pin-programmed for lithium-ion/polymer battery packs of 1-, 2-, 3- or 4-series cells. The LTC4009-1 provides output voltage of 4.1V/cell, and the LTC4009-2 is a 4.2V/cell version. The device includes AC adapter input current limiting which maximizes the charge rate for a fixed input power level. An external sense resistor programs the input current limit, and the ICL status pin indicates when the battery charge current is being reduced as a result of AC adapter current limiting. The CHRG status pin is active during all charging modes, including special indication for low charge current.
General Purpose Battery Charger Controller Efficient 550kHz Synchronous Buck PWM Topology 0.5% Output Float Voltage Accuracy Programmable Charge Current: 4% Accuracy Programmable AC Adapter Current Limit: 3% Accuracy No Audible Noise with Ceramic Capacitors Wide Input Voltage Range: 6V to 28V Wide Output Voltage Range: 2V to 28V Indicator Outputs for AC Adapter Present, Charging, C/10 Current Detection and Input Current Limiting Analog Charge Current Monitor Micropower Shutdown Thermally Enhanced 20-Pin 4mm x 4mm x 0.75mm QFN Package
APPLICATIONS
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Notebook Computers Portable Instruments Battery Backup Systems
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5723970.
TYPICAL APPLICATION
FROM ADAPTER 13V TO 20V 33m 0.1F DCIN 14.3k CLP 0.1F 5.1k
100
20F
POWER TO SYSTEM
Efficiency at DCIN = 20V
10000 95 EFFICIENCY (%) 90 POWER LOSS 85 80 75 70 VFLOAT = 12.3V RSENSE = 33m RIN = 3.01k RPROG = 26.7k DIN = SSB44 L = IHLP-2525CZ 6.8H 0 0.5 1.0 1.5 2.0 CHARGE CURRENT (A) 2.5 100 3.0 1000
1.5k
CLN DCDIV BOOST LTC4009 TGATE CHRG SW INTVDD BGATE GND
0.1F
EFFICIENCY POWER LOSS (mW)
TO/FROM MCU
ACP ICL SHDN ITH 6.04k 0.1F
2F
6.8H
3.01k CSP 33m 3.01k CSN BAT PROG 4.7nF 26.7k VFB 32.8k FBDIV 301k 20F
CHARGE CURRENT MONITOR
+
12.3V Li-Ion BATTERY
4009 TA01a
4009 TA01b
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LTC4009 LTC4009-1/LTC4009-2 ABSOLUTE MAXIMUM RATINGS
(Note 1)
DCIN, CLP CLN or SW to GND ................... -0.3V to 30V , CLP to CLN ............................................................0.3V CSP CSN or BAT to GND ............................ -0.3V to 28V , CSP to CSN ............................................................0.3V BOOST to GND ........................................... -0.3V to 36V BOOST to SW............................................... -0.3V to 7V
DCDIV, SHDN, FVS0, FVS1 or VFB to GND .... -0.3V to 7V ACP, CHRG or ICL to GND ......................... -0.3V to 30V Operating Temperature Range (Note 2)........ 0C to 85C Junction Temperature (Note 3) ............................. 125C Storage Temperature Range................... -65C to 150C
PIN CONFIGURATION
LTC4009
BOOST TOP VIEW INTVDD BGATE TGATE SW INTVDD BOOST BGATE 15 CSP 14 CSN 21 13 PROG 12 ITH 11 BAT 6 SHDN 7 ACP 8 CHRG 9 10 FVS0 FVS1 TGATE
LTC4009-1 LTC4009-2
TOP VIEW SW
20 19 18 17 16 CLN 1 CLP 2 DCIN 3 ICL 4 DCDIV 5 6 SHDN 7 ACP 8 CHRG 9 10 FBDIV VFB 21 15 CSP 14 CSN 13 PROG 12 ITH 11 BAT CLN 1 CLP 2 DCIN 3 ICL 4 DCDIV 5
20 19 18 17 16
UF PACKAGE 20-LEAD (4mm 4mm) PLASTIC QFN TJMAX = 125C, JA = 37C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
UF PACKAGE 20-LEAD (4mm 4mm) PLASTIC QFN TJMAX = 125C, JA = 37C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC4009CUF#PBF LTC4009CUF-1#PBF LTC4009CUF-2#PBF TAPE AND REEL LTC4009CUF#TRPBF LTC4009CUF-1#TRPBF LTC4009CUF-2#TRPBF PART MARKING 4009 40091 40092 PACKAGE DESCRIPTION 20-Lead (4mm x 4mm) Plastic QFN 20-Lead (4mm x 4mm) Plastic QFN 20-Lead (4mm x 4mm) Plastic QFN TEMPERATURE RANGE 0C to 85C 0C to 85C 0C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC4009 LTC4009-1/LTC4009-2 ELECTRICAL CHARACTERISTICS
SYMBOL VTOL PARAMETER VBAT Accuracy (See Test Circuits) Charge Voltage Regulation LTC4009 LTC4009-1/LTC4009-2 IVFB RON ILEAK-FBDIV VBOV VFB Input Bias Current FBDIV On-Resistance FBDIV Output Leakage Current VFB Overvoltage Threshold BAT Overvoltage Threshold Charge Current Regulation ITOL Charge Current Accuracy with RIN = 3.01k, 5V < BAT < 18V Current Sense Amplifier Gain (PROG I) with RIN = 3.01k, 5V < BAT < 18V RPROG = 26.7k VSENSE = 0mV, PROG = 1.2V AI VCS-MAX VC10 VREV VCL ICLN VICL OVR IDCO ICLPO VCBT VCNT VOVP Shutdown VACP VACP(HYST) IDCDIV VIL VIH RIN IDCS ICLPS DCDIV AC Present Threshold Voltage DCDIV ACP Threshold Hysteresis Voltage DCDIV Input Current SHDN Input Voltage Low SHDN Input Voltage High SHDN Pull-Down Resistance DCIN Shutdown Current CLP Shutdown Current SHDN = 0V CLP = 12V, SHDN = 0V or DCDIV = 0V
l l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. DCIN = 20V, BAT = 12V, GND = 0V unless otherwise noted.
CONDITIONS MIN -0.5 -0.8 -0.6 -0.8 20 85 -1 1.235 103 0 1.281 106 190 1 1.32 109 TYP MAX 0.5 0.8 0.6 0.8 UNITS % % % % nA A V %
VFB = 1.2V ILOAD = 100A SHDN = 0V, FBDIV = 0V LTC4009 LTC4009-1/LTC4009-2, Relative to Selected Output Voltage
-4 -5 -12.75 -1.78 -11.67 -1.66 185 325 400 253 100 100 100 -8 6 1.5 0.5 -5
4 5 -10.95 -1.54 235 430 460 295 103 104 -2 28 2 0.8 60 60 1.9
% % A A mV mV mV mV mV mV nA mV V mA mA mV mV V mV
VSENSE Step from 0mV to 5mV, PROG = 1.2V
l l
Maximum Peak Current Sense Threshold Voltage ITH = 2V per Cycle (RIN = 3.01k) ITH = 5V C/10 Indicator Threshold Voltage Reverse Current Threshold Voltage Current Limit Threshold CLN Input Bias Current ICL Indicator Threshold Operating Voltage Range DCIN Operating Current CLP Operating Current CLP Boost Threshold Voltage CLP Normal Threshold Voltage (Note 5) DCDIV Overvoltage Protection Threshold PROG Falling PROG Falling CLP - CLN CLN = CLP (CLP - CLN) - VCL DCIN and CLP No Gate Loads CLP = 20V, No Gate Loads CLP - DCIN, CLP Rising DCIN - CLP CLP Falling , DCDIV Rising
140 340 180 97 96
Input Current Regulation
l
DCIN, CLP Supplies
l l
10 10 1.75
25 25 1.825 110
VOVP(HYST) DCDIV OVP Threshold Hysteresis DCDIV Rising DCDIV = 1.2V
l l l
1.145 -1 1.4
1.2 50 0
1.255 1 300
V mV A mV V k A
50 215 9 18
A
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LTC4009 LTC4009-1/LTC4009-2 ELECTRICAL CHARACTERISTICS
SYMBOL ILEAK-BAT ILEAK-CSN ILEAK-CSP ILEAK-SW PARAMETER BAT Leakage Current CSN Leakage Current CSP Leakage Current SW Leakage Current
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. DCIN = 20V, BAT = 12V, GND = 0V unless otherwise noted.
CONDITIONS SHDN = 0V or DCDIV = 0V, 0V CSP = CSN = BAT 20V SHDN = 0V or DCDIV = 0V, 0V CSP = CSN = BAT 20V SHDN = 0V or DCDIV = 0V, 0V CSP = CSN = BAT 20V SHDN = 0V or DCDIV = 0V, 0V SW 20V No Load IDD = 20mA INTVDD = 0V CLP - BAT, CLP Rising ITH = 1.4V 467 CLOAD = 3.3nF CLOAD = 3.3nF CLOAD = 3.3nF 10% - 90% , CLOAD = 3.3nF 90% - 10% , CLOAD = 3.3nF 10% - 90% , CLOAD = 3.3nF 90% - 10% , CLOAD = 3.3nF 10% - 10% , 20 98
l l l l l
MIN -1 -1 -1 -1
TYP 0 0 0 0
MAX 1 1 1 2
UNITS A A A A
INTVDD Regulator INTVDD VDD IDD VCE IITH fTYP fMIN DCMAX tR-TG tF-TG tR-BG tF-BG tNO VIL VIH IIN VOL ILEAK IC10 Output Voltage Load Regulation Short-Circuit Current (Note 6) Charge Enable Threshold Voltage ITH Current Typical Switching Frequency Minimum Switching Frequency Maximum Duty Cycle TGATE Rise Time TGATE Fall Time BGATE Rise Time BGATE Fall Time TGATE, BGATE Non-Overlap Time Input Voltage Low Input Voltage High Input Current Output Voltage Low Output Leakage CHRG C/10 Current Sink 0V VIN 5V ILOAD = 100A, PROG = 1.2V SHDN = 0V, DCDIV = 0V, VOUT = 20V CHRG = 2.5V
l l l
4.85 50 65
5 -0.4 85 100 -40/+90 550 25 99 60 50 60 60 110
5.15 -1 120 135 633
V % mA mV A kHz kHz %
Switching Regulator
110 90 90 110
ns ns ns ns ns
Float Voltage Select Inputs (LTC4009-1/LTC4009-2 Only) 0.5 3.5 -10 10 500 -10 15 25 10 38 V V A mV A A
Indicator Outputs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC4009 is guaranteed to meet performance specifications over the 0C to 85C operating temperature range. Note 3: Operating junction temperature TJ (in C) is calculated from the ambient temperature TA and the total continuous package power dissipation PD (in watts) by the formula TJ = TA + (JA * PD). Refer to the Applications Information section for details.
Note 4: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to GND, unless otherwise specified. Note 5: This threshold is guaranteed to be satisfied if CLP = DCIN when the LTC4009 exits shutdown. Note 6: Output current may be limited by internal power dissipation. Refer to the Applications Information section for details.
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LTC4009 LTC4009-1/LTC4009-2 TEST CIRCUITS
LTC4009 FROM ICL (CLP = CLN) LTC4009-1 LTC4009-2 FROM ICL (CLP = CLN)
1.2085V
- - - +
EA 1.2085V
- - - +
EA
PROG 13
VFB 10 1.2085V TARGET
ITH 12
PROG 13
BAT 11 TARGET VARIES WITH FVS0,1
ITH 12
+
LTC1055
+
LTC1055
-
4009 TC01
0.6V
-
4009 TC02
0.6V
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25C unless otherwise noted. DIN = SSB44, L = IHLP-2525 6.8H) Efficiency at DCIN = 20V, BAT = 8V
100 RSENSE = 33m RIN = 3.01k 10000 100
Efficiency at DCIN = 20V, BAT = 12V
RSENSE = 33m RIN = 3.01k POWER LOSS EFFICIENCY 90 1000 10000
95 EFFICIENCY (%) POWER LOSS 90 EFFICIENCY 85 1000
95 EFFICIENCY (%)
POWER LOSS (mW)
POWER LOSS (mW)
85
80 0 0.5 1.0 1.5 2.0 CHARGE CURRENT (A) 2.5
100 3.0
4009 G01
80 0 0.5 1.0 1.5 2.0 CHARGE CURRENT (A) 2.5
100 3.0
4009 G02
Efficiency at DCIN = 20V, BAT = 16V
100 RSENSE = 33m RIN = 3.01k EFFICIENCY 10000 0.10 0.08 0.06 POWER LOSS (mW) VFB ERROR (%) 0.04
VFB Line Regulation
LTC4009 TEST CIRCUIT 300 275 250 225 RON () 200 175 150 125 100 5 10 20 15 CLP (V) 25 30
4009 G04
FBDIV RON vs BAT
CLP = BAT + 3V (CLP 6V)
95 EFFICIENCY (%)
POWER LOSS 90 1000
0.02 0 -0.02 -0.04 -0.06 -0.08
85
80 0 0.5 1.0 1.5 2.0 CHARGE CURRENT (A) 2.5
100 3.0
4009 G03
-0.10
75 0 5 15 10 BAT (V) 20 25
4009 G05
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LTC4009 LTC4009-1/LTC4009-2 TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25C unless otherwise noted. DIN = SSB44, L = IHLP-2525 6.8H) Battery Load Dump
5 BATTERY VOLTAGE (500mV/DIV) CHARGE CURRENT ERROR (%) 2A 12.1V 1A 3A RECONNECT DISCONNECT CLP = 20V TIME (1ms/DIV) VFLOAT = 12.3V
4009 G06
Charge Current Accuracy
4 3 2 1 0 -1 -2 DCIN = 12V RPROG = 26.7k 0 2 4 6 8 10 12 14 16 18 20 22 24 BAT (V)
4009 G15
Charge Current Line Regulation
0.5 0.4 CHARGE CURRENT ERROR (%) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 5 10 15 DCIN (V) 20 25
4009 G07
RSENSE = 33m RIN = 3.01k DCIN = 24V RPROG = 35.7k
BAT = 6V RSENSE = 33m RIN = 3.01k ICHG = 1A
1A
ICHG = 2A ICHG = 3A
LOAD STATE
Charge Current Load Regulation
3.5 3.0 CHARGE CURRENT (A) 2.5 CURRENT (A) 2.0 1.5 1.0 0.5 0 DCIN = 20V RSENSE = 33m RIN = 3.01k 11.4 11.8 12.2 BAT (V) 12.6 13.0
4009 G08
Input Current Limit
3.0 2.5 2.0 ICHG 2A/DIV ITH 1V/DIV PROG 1V/DIV SHDN 5V/DIV
PWM Soft-Start
ICHG = 3A
IIN ICHG
ICHG = 2A
1.5 1.0 0.5 0 -0.5 -1.0 0 0.5
ICHG = 1A
2.5A BULK CHARGE 2.1A INPUT CURRENT LIMIT
ICL STATE 1.0 1.5 SYSTEM LOAD (A) 2.0 2.5
4009 G09
TIME (500s/DIV)
4009 G10
-0.5 11.0
Gate Drive Non-Overlap
600 EXTERNAL FET DRIVE (1V/DIV) BGATE PWM FREQUENCY (kHz) 500 400 300 200 100 0
PWM Frequency vs Duty Cycle
ICHG = 750mA
TGATE
TIME (80ns/DIV)
4009 G11
CLP = 6V CLP = 12V CLP = 20V CLP = 25V 0 20 40 60 DUTY CYCLE (%) 80 100
4009 G12
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LTC4009 LTC4009-1/LTC4009-2 TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25C unless otherwise noted. DIN = SSB44, L = IHLP-2525 6.8H) PWM Frequency vs Charge Current
600 500 PWM FREQUENCY (kHz) 400 300 200 100 0 BAT = 14.5V CLP = 15V RSENSE = 33m RIN = 3.01k BAT = 5V BAT = 12V BATTERY CURRENT (A) 20 DC1104 WITH SSB44 INPUT DIODE LTC4009 ALL PINS 10 25
Battery Shutdown Current
15
5
0 0 0.5 1.0 1.5 2.0 CHARGE CURRENT (A) 2.5 3.0
4009 G13
0
5
15 20 10 BATTERY VOLTAGE (V)
25
4009 G14
PIN FUNCTIONS
CLN (Pin 1): Adapter Input Current Limit Negative Input. The LTC4009 senses voltage on this pin to determine if the charge current should be reduced to limit total input current. The threshold is set 100mV below the CLP pin. An external filter should be used to remove switching noise. This input should be tied to CLP if not used. Operating voltage range is (CLP - 110mV) to CLP . CLP (Pin 2): Adapter Input Current Limit Positive Input. The LTC4009 also draws power from this pin, including a small amount for some shutdown functions. Operating voltage range is GND to 28V. DCIN (Pin 3): DC Power Input. The LTC4009 draws power from this pin when an external DC power source is present. This pin is typically isolated from the CLP pin by a diode and should be bypassed with a capacitance of 0.1F or more. Operating voltage range is GND to 28V. ICL (Pin 4): Active-Low Input Current Limit Indicator Output. This open-drain output pulls to GND when the charge current is reduced because of AC adapter input current limiting. This output should be left floating if not used. DCDIV (Pin 5): AC Adapter Present Comparator Input. The LTC4009 senses voltage on this pin to determine when an adequate DC power source is present, or if an overvoltage condition exists. An external resistor divider programs these threshold levels relative to DCIN. Operating voltage range is GND to INTVDD. SHDN (Pin 6): Active-low Shutdown Input. Driving SHDN below 300mV unconditionally forces the LTC4009 into the shutdown state. This input has a 50k internal pulldown to GND. Operating voltage range is GND to INTVDD. ACP (Pin 7): Active-Low AC Adapter Present Indicator Output. This open-drain output pulls to GND when adequate AC adapter (DC) voltage is present, based on the DCDIV input. This output should be left floating if not used. CHRG (Pin 8): Active-Low Charge Indicator Output. This open-drain output provides three levels of information about charge status using a strong pull-down, 25A weak pull-down or high impedance. Refer to the Operation and Applications Information sections for further details. This output should be left floating if not used. FBDIV (Pin 9, LTC4009): Battery Voltage Feedback Resistor Divider Source. The LTC4009 connects this pin to BAT when charging is in progress. FBDIV is an open-drain PFET output to BAT with an operating voltage range of GND to BAT.
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LTC4009 LTC4009-1/LTC4009-2 PIN FUNCTIONS
FVS0 (Pin 9, LTC4009-1/LTC4009-2): Battery Voltage Select Input (LSB). This pin is one of two pins used on the LTC4009-1 or LTC4009-2 to select one of four preset battery voltages. Selection is done by connecting to either GND or INTVDD. Operating voltage range is GND to INTVDD. VFB (Pin 10, LTC4009): Battery Voltage Feedback Input. An external resistor divider between FBDIV and GND with the center tap connected to VFB programs the charger output voltage. In constant voltage mode, this pin is nominally at 1.2085V. Refer to the Applications Information section for complete details on programming battery float voltage. Operating voltage range is GND to 1.25V. FVS1 (Pin 10, LTC4009-1/LTC4009-2): Battery Voltage Select Input (MSB). This pin is one of two pins used on the LTC4009-1 or LTC4009-2 to select one of four preset battery voltages. Selection is done by connecting to either GND or INTVDD. Operating voltage range is GND to INTVDD. BAT (Pin 11): Battery Pack Connection. The LTC4009 uses the voltage on this pin to control PWM operation when charging. Operating voltage range is GND to CLN. ITH (Pin 12): PWM Control Voltage and Compensation Node. The LTC4009 develops a voltage on this pin to control cycle-by-cycle peak inductor current. An external R-C network connected to ITH provides PWM loop compensation. Refer to the Applications Information section for further details on establishing loop stability. Operating voltage range is GND to INTVDD. PROG (Pin 13): Charge Current Programming and Monitoring Pin. An external resistance connected between PROG and GND, along with the current sense and PWM input resistors, programs the maximum charge current. The voltage on this pin can also provide a linearized indicator of charge current. Refer to the Applications Information section for complete details on current programming and monitoring. Operating voltage range is GND to INTVDD. CSN (Pin 14): Charge Current Sense Negative Input. Place an external input resistor (RIN, Figure 1) between this pin and the negative side of the charge current sense resistor. Operating voltage ranges from (BAT - 50mV) to (BAT + 200mV). CSP (Pin 15): Charge Current Sense Positive Input. Place an external input resistor (RIN, Figure 1) between this pin and the positive side of the charge current sense resistor. Operating voltage ranges from (BAT - 50mV) to (BAT + 200mV). BGATE (Pin 16): External Synchronous NFET Gate Control Output. This output provides gate drive to an external NMOS power transistor switch used for synchronous rectification to increase efficiency in the step-down DC/DC converter. Operating voltage is GND to INTVDD. BGATE should be left floating if not used. INTVDD (Pin 17): Internal 5V Regulator Output. This pin provides a means of bypassing the internal 5V regulator used to power the LTC4009 PWM FET drivers. This supply shuts down when the LTC4009 shuts down. Refer to the Application Information section for details if additional power is drawn from this pin by the application circuit. SW (Pin 18): PWM Switch Node. The LTC4009 uses the voltage on this pin as the source reference for its topside NFET (PWM switch) driver. Refer to the Applications Information section for additional PCB layout suggestions related to this critical circuit node. Operating voltage range is GND to CLN. TGATE (Pin 19): External NFET Switch Gate Control Output. This output provides gate drive to an external NMOS power transistor switch used in the DC/DC converter. Operating voltage range is GND to (CLN + 5V). BOOST (Pin 20): TGATE Driver Supply Input. A bootstrap capacitor is returned to this pin from a charge network connected to SW and INTVDD. Refer to the Applications Information section for complete details on circuit topology and component values. Operating voltage ranges from (INTVDD - 1V) to (CLN + 5V). Exposed Pad (Pin 21): Ground. The package paddle provides a single-point ground for the internal voltage reference and other critical LTC4009 circuits. It must be soldered to a suitable PCB copper ground pad for proper electrical operation and to obtain the specified package thermal resistance.
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LTC4009 LTC4009-1/LTC4009-2 BLOCK DIAGRAM
3 DCIN BOOST AND OV DETECTION CLP CLN ICL CHRG VFB CA C/10 DETECTION INPUT CURRENT LIMIT
(LTC4009)
2 1 4 8
10
+ +
CC R1
CSP
15
-
EA
CSN
14
-
TO INTERNAL CIRCUITS
11
BAT
OSCILLATOR TGATE TO INTERNAL CIRCIUTS 5V REGULATOR SW INTVDD BGATE GND
CHARGE
9 FBDIV DCDIV ACP SHDN TO INTERNAL CIRCUITS
OVERVOLTAGE
5 7 6
SHUTDOWN CONTROL
SHUTDOWN
+ - - -
1.2085V REFERENCE PWM LOGIC
PROG
13
ITH BOOST
12 20 19 18
17 16 21
4009 BD01
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LTC4009 LTC4009-1/LTC4009-2 BLOCK DIAGRAM
3 DCIN BOOST AND OV DETECTION CLP CLN ICL CHRG C/10 DETECTION VFB OUTPUT VOLTAGE SELECT CC CA INPUT CURRENT LIMIT
(LTC4009-1/LTC4009-2)
2 1 4 8
10 9 11
FVS1 FVS0 BAT
+ -
R1 EA
CSP
15
+ - + - - -
1.2085V REFERENCE PWM LOGIC
CSN
14
PROG
13
TO INTERNAL CIRCUITS
ITH BOOST OSCILLATOR TGATE TO INTERNAL CIRCIUTS 5V REGULATOR SW INTVDD BGATE GND 5 7 6 DCDIV ACP SHDN SHUTDOWN CONTROL SHUTDOWN TO INTERNAL CIRCUITS
12 20 19 18
CHARGE
17 16 21
OVERVOLTAGE
4009 BD02
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LTC4009 LTC4009-1/LTC4009-2 OPERATION
Overview The LTC4009 is a synchronous step-down (buck) current mode PWM battery charger controller. The maximum charge current is programmed by the combination of a charge current sense resistor (RSENSE), matched input resistors (RIN, Figure 1), and a programming resistor (RPROG) between the PROG and GND pins. Battery voltage is programmed either with an external resistor divider between FBDIV and GND (LTC4009) or two digital battery voltage select pins (LTC4009-1/LTC4009-2). In addition, the PROG pin provides a linearized voltage output of the actual charge current. The LTC4009 family does not have any built-in charge termination and is flexible enough for charging any type of battery chemistry. These are building block ICs intended for use with an external circuit, such as a microcontroller, capable of managing the entire algorithm required for the specific battery being charged. Each member of the LTC4009 family features a shutdown input and various state indicator outputs, allowing easy and direct management by a wide range of external (digital) charge controllers. Due to the popularity of rechargeable lithium-ion chemistries, the LTC4009-1 and LTC4009-2 also offer internal precision resistors that can be digitally selected to produce one of four preset output voltages for simplified design of those charger types. Shutdown The LTC4009 remains in shutdown until DCDIV exceeds 1.2V, and SHDN is driven above 1.4V. In shutdown, current drain from the battery is reduced to the lowest possible level, thereby increasing standby time. When in shutdown, the ITH pin is pulled to GND and the CHRG, ICL, FET gate drivers and INTVDD output are all disabled. The ACP status output indicates sensed adapter input voltage during all LTC4009 states. Charging can be stopped at any time by forcing SHDN below 300mV. Soft-Start Exiting the shutdown state enables the charger and releases the ITH pin. When enabled, switching will not begin until CLP exceeds BAT by 100mV and ITH exceeds a threshold that assures initial current will be positive (about 5% to 25% of the maximum programmed current). To limit inrush current, soft-start delay is created with the compensation values used on the ITH pin. Longer soft-start times can be realized by increasing the filter capacitor on ITH, if reduced loop bandwidth is acceptable. The actual charge current at the end of soft-start will depend on which loop (current, voltage or adapter limit) is in control of the PWM. If this current is below that required by the ITH start-up threshold, the resulting charge current transient duration depends on loop compensation but is typically less than 100s. Bulk Charge When soft-start is complete, the LTC4009 begins sourcing the current programmed by the external components connected to CSP CSN and PROG. Some batteries may , require a small conditioning trickle current if they are heavily discharged. As shown in the Applications Information section, the LTC4009 can address this need through a variety of low current circuit techniques on the PROG pin. Once a suitable cell voltage has been reached, charge current can be switched to a higher, bulk charge value. End-of-Charge and CHRG Output As the battery approaches the programmed output voltage, charge current will begin to decrease. The opendrain CHRG output can indicate when the current drops to 10% of its programmed full-scale value by turning off the strong pull-down (open-drain FET) and turning on a weak 25A pull-down current. This weak pull-down state is latched until the part enters shutdown or the sensed current rises to roughly C/6. C/10 indication will not be set if charge current has been reduced due to adapter input current limiting or DCIN/battery overvoltage. As the charge current approaches 0A, the PWM continues to operate in full continuous mode. This avoids generation of audible noise, allowing bulk ceramic capacitors to be used in the application.
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LTC4009 LTC4009-1/LTC4009-2 OPERATION
LTC4009 WATCHDOG TIMER SYSTEM POWER 2 11 CLP BAT OSCILLATOR CLOCK S RD Q PWM LOGIC TGATE 19 L1 BGATE 16 RIN 15 RIN 14 13 RPROG CPROG
+ +
CC R1 CA
CSP
+
RSENSE VSENSE
-
CSN PROG
-
-
ICHRG
EA
Figure 1. PWM Circuit Diagram
Charge Current Monitoring When the LTC4009 is charging, the voltage on the PROG pin varies in direct proportion to the charge current. Referring to Figure 1, the nominal PROG voltage is given by VPROG = ICHRG * RSENSE * RPROG + 11.67A * RPROG RIN
Voltage tolerance on PROG is limited by the charge current accuracy specified in the Electrical Characteristics table. Refer to the Applications Information section on programming charge current for additional details. Adapter Input Current Limit The LTC4009 can monitor and limit current from the input DC supply, which is normally an AC adapter. When the programmed adapter input current is reached, charge current is reduced to maintain the desired maximum input current. The ITH and PROG pins will reflect the reduced charge current. This limit function avoids overloading the DC input source, allowing the product to operate at the same time the battery is charging without complex load
12
+ - - -
FROM ICL 1.2085V
VFB
+
10
ITH
12
LOOP COMPENSATION
4009 F01
management algorithms. The battery will automatically be charged at the maximum possible rate that the adapter will support, given the application's operating condition. The LTC4009 can only limit input current by reducing charge current, and in this case the charger uses nonsynchronous PWM operation to prevent boosting if the average charge current falls below about 25% of the maximum programmed current. Note that the ICL indicator output becomes active (low) at an adapter input current level just slightly less than that required for the internal amplifier to begin to assert control over the PWM loop. If system load current equals or exceeds the input adapter current limit for more than a few milliseconds, the bootstrap capacitor between BOOST and SW can fully discharge due to normal pin leakage currents. In this case, the PWM will not restart until the system current has dropped to about 85% of the programmed input adapter limit value. Charger Status Indicator Outputs The LTC4009 open-drain indicator outputs provide valuable information about the IC's operating state and can
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LTC4009 LTC4009-1/LTC4009-2 OPERATION
be used for a variety of purposes in applications. Table 1 summarizes the state of the three indicator outputs as a function of LTC4009 operation.
Table 1. LTC4009 Open-Drain Indicator Outputs
ACP Off On On On On On On CHRG Off Off On 25A On 25A Off ICL Off Off Off Off On On On CHARGER STATE No DC Input (Shutdown) Shutdown, Reverse Current or DCIN Overvoltage Bulk Charge Low Current Charge or Initial CLP-BAT < 100mV Input Current Limit During Bulk Charge Input Current Limit During Low Current Charge Input Current Limit During DCIN Overvoltage
receives loop control information from the battery voltage feedback input VFB and the adapter input current limit circuit. The ITH output of the error amplifier is a scaled control voltage for one input of the PWM comparator CC. ITH sets a peak inductor current threshold, sensed by R1, to maintain the desired average current through RSENSE. The current comparator output does this by switching the state of the RS latch at the appropriate time. At the beginning of each oscillator cycle, the PWM clock sets the RS latch and turns on the external topside NFET (bottom-side synchronous NFET off) to refresh the current carried by the external inductor L1. The inductor current and voltage across RSENSE begin to rise linearly. CA buffers this instantaneous voltage rise and applies it to CC with gain supplied by R1. When the voltage across R1 exceeds the peak level set by the ITH output of EA, the top FET turns off and the bottom FET turns on. The inductor current then ramps down linearly until the next rising PWM clock edge. This closes the loop and sources the correct inductor current to maintain the desired parameter (charge current, battery voltage, or input current). To produce a near constant frequency, the PWM oscillator implements the equation: tOFF = CLP - BAT CLP * 550kHz
PWM Controller The LTC4009 uses a synchronous step-down architecture to produce high operating efficiency. The nominal operating frequency of 550kHz allows use of small filter components. The following conceptual discussion of basic PWM operation references Figure 1. The voltage across the external charge current sense resistor RSENSE is measured by current amplifier CA. This instantaneous current (VSENSE/RIN) is fed to the PROG pin where it is averaged by an external capacitor and converted to a voltage by the programming resistor RPROG between PROG and GND. The PROG voltage becomes the average charge current input signal to error amplifier EA. EA also
ON TOP FET OFF ON BOTTOM FET OFF tOFF
Repetitive, closed-loop waveforms for stable PWM operation appear in Figure 2.
INDUCTOR CURRENT
THRESHOLD SET BY ITH VOLTAGE
4009 F02
Figure 2. PWM Waveforms
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LTC4009 LTC4009-1/LTC4009-2 OPERATION
PWM Watchdog Timer As input and output conditions vary, the LTC4009 may need to utilize PWM duty cycles approaching 100%. In this case, operating frequency may be reduced well below 550kHz. An internal watchdog timer observes the activity on the TGATE pin. If TGATE is on for more than 40s, the watchdog activates and forces the bottom NFET on (top NFET off) for about 100ns. This avoids a potential source of audible noise when using ceramic input or output capacitors and prevents the boost supply capacitor for the top gate driver from discharging. In low drop out operation, the actual charge current may not be able to reach the programmed full-scale value due to the watchdog function. Overvoltage Protection The LTC4009 also contains overvoltage detection that prevents transient battery voltage overshoots of more than about 6% above the programmed output voltage. When battery overvoltage is detected, both external MOSFETs are turned off until the overvoltage condition clears, at which time a new soft start sequence begins. This is useful for properly charging battery packs that use an internal switch to disconnect themselves for performing functions such as calibration or pulse mode charging. Reverse Charge Current Protection (Anti-Boost) Because the LTC4009 always attempts to operate synchronously in full continuous mode (to avoid audible noise from ceramic capacitors), reverse average charge current can occur during some invalid operating conditions. To avoid boosting a lightly loaded system supply during reverse operation, the LTC4009 monitors the voltage on CLP to determine if it rises 25mV above DCIN during charge. However, under heavier system loads, CLP may not boost above DCIN, even though reverse average current is flowing. In this case a second circuit monitors indication of reverse average current on PROG. If the designer intends to replace the input diode with a MOSFET for improved efficiency, using the ACP signal of the LTC4009 to control the MOSFET is not recommended. In this case, the LTC4012 is strongly suggested, because it includes ideal diode control of the MOSFET, instead of driving it as a simple switch. This solution is the most effective at detecting boost conditions and quickly shutting down the IC. If for some reason the LTC4012 solution is not acceptable, and a MOSFET with external control is used to replace the input diode, and there are conditions involving very low reverse current under no system load with an AC adapter that cannot sink current, it may still be possible to boost the DCIN input supply. To cover this case, the LTC4009 monitors the resistor divider attached to the DCDIV pin and sets an input overvoltage fault if that voltage exceeds 1.825V. If any of these circuits detects boost operation, The LTC4009 turns off both external MOSFETs until the reverse current condition clears. Once DCIN-CLP > 25mV, a new soft-start sequence begins.
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LTC4009 LTC4009-1/LTC4009-2 APPLICATIONS INFORMATION
Programming Charge Current The formula for charge current is: ICHRG = RIN RSENSE 1.2085V * - 11.67A RPROG The resistance between PROG and GND can simply be set with a single a resistor, if only maximum charge current needs to be controlled during the desired charging algorithm. However, some batteries require a low charge current for initial conditioning when they are heavily discharged. The charge current can then be safely switched to a higher level after conditioning is complete. Figure 3 illustrates one method of doing this with 2-level control of the PROG pin resistance. Turning Q1 off reduces the charge current to IMAX/10 for battery conditioning. When Q1 is on, the LTC4009 is programmed to allow full IMAX current for bulk charge. This technique can be expanded through the use of additional digital control inputs for an arbitrary number of pre-programmed current values.
LTC4009 PROG 13
The LTC4009 operates best with 3.01k input resistors, although other resistors near this value can be used to accommodate standard sense resistor values. Refer to the subsequent discussion on inductor selection for other considerations that come into play when selecting input resistors RIN. RSENSE should be chosen according to the following equation: RSENSE = 100mV IMAX
where IMAX is the desired maximum charge current ICHRG. The 100mV target can be adjusted to some degree to obtain standard RSENSE values and/or a desired RPROG value, but target voltages lower than 100mV will cause a proportional reduction in current regulation accuracy. The required minimum resistance between PROG and GND can be determined by applying the suggested expression for RSENSE while solving the first equation given above for charge current with ICHRG = IMAX: 1.2085V * RIN RPROG(MIN) = 0.1V + 11.67A * RIN If RIN is chosen to be 3.01k with a sense voltage of 100mV, this equation indicates a minimum value for RPROG of 26.9k. Table 6 gives some examples of recommended charge current programming component values based on these equations.
BULK CHARGE PRECHARGE
R1 26.7k Q1 2N7002 R2 53.6k
4009 F03
CPROG 4.7nF
Figure 3. Programming 2-Level Charge Current
For a truly continuous range of maximum charge current control, pulse width modulation can be used as shown in Figure 4. The value of RPROG controls the maximum value of charge current which can be programmed (Q1 continuously on). PWM of the Q1 gate voltage changes the value of RPROG to produce lower currents. The frequency of this modulation should be higher than a few kHz, and CPROG must be increased to reduce the ripple caused by switching Q1. In addition, it may be necessary to increase loop
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LTC4009 LTC4009-1/LTC4009-2 APPLICATIONS INFORMATION
BAT LTC4009 PROG 13 LTC4009 RPROG 5V 0V CPROG Q1 2N7002
4009 F04
95 TYPICAL FBDIV
11
9 R1 CZ
RMAX 511k
+
VFB 10 R2A GND (EXPOSED PAD) 21
4009 F05
R2B*
*OPTIONAL TRIM RESISTOR
Figure 4. Programming PWM Current
Figure 5. Programming LTC4009 Output Voltage
compensation capacitance connected to ITH to maintain stability or prevent large current overshoot during startup. Selecting a higher Q1 PWM frequency (10kHz) will reduce the need to change CPROG or other compensation values.Charge current will be proportional to the duty cycle of the PWM input on the gate of Q1. Programming LTC4009 Output Voltage Figure 5 shows the external circuit for programming the charger voltage when using the LTC4009. The voltage is then governed by the following equation: VBAT = 1.2085V * (R1+ R2) , R2 = R2A + R2B R2
required. Actually, the temperature rise of the LTC4009 will rarely exceed 50C at the end of charge, because charge current will have tapered to a low level. This means that 0.25% resistors will normally provide the required level of overall accuracy. Table 2 gives recommended values for R1 and R2 for popular lithium-ion battery voltages. For values of R1 above 200k, addition of capacitor CZ may improve transient response and loop stability. A value of 10pF is normally adequate.
Table 2. Programming LTC4009 Output Voltage
VBAT VOLTAGE 4.1V 4.2V 8.2V 8.4V 12.3V 12.6V 16.4V 16.8V 20.5V 21.0V 24.6V 25.2V R1 (0.25%) 165k 167k 162k 169k 301k 294k 284k 271k 316k 298k 298k 397k R2A (0.25%) 69.0k 67.3k 28.0k 28.4k 32.8k 31.2k 22.6k 21.0k 19.8k 18.2k 15.4k 20.0k R2B (1%)* - 200 - - - - - - - - - -
See Table 2 for approximate resistor values for R2. V R1 = R2 BAT - 1 , R2 = R2A + R2B 1.2085V Selecting R2 to be less than 50k and the sum of R1 and R2 at least 200k or above, achieves the lowest possible error at the VFB sense input. Note that sources of error such as R1 and R2 tolerance, FBDIV RON or VFB input impedance are not included in the specifications given in the Electrical Characteristics. This leads to the possibility that very accurate (0.1%) external resistors might be
*To obtain required accuracy requires series resistors for R2.
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LTC4009 LTC4009-1/LTC4009-2 APPLICATIONS INFORMATION
Programming LTC4009-1/LTC4009-2 Output Voltage The LTC4009-1/LTC4009-2 feature precision internal battery voltage feedback resistor taps configured for common lithium-ion voltages. All that is required to program the desired voltage is proper pin programming of FVS0 and FVS1 as shown in Table 3.
Table 3. LTC4009-1/LTC4009-2 Output Voltage Programming
VBAT VOLTAGE LTC4009-1 4.1V 8.2V 12.3V 16.4V LTC4009-2 4.2V 8.4V 12.6V 16.8V FVS1 GND GND INTVDD INTVDD FVS0 GND INTVDD GND INTVDD
FROM DC POWER INPUT CDC 10k RCL CF 0.1F RF 5.1k TO REMAINDER OF SYSTEM
2 CLP
1 CLN LTC4009
4009 F06
Figure 6. Programming Input Current Limit Table 4. Common RCL Values
ADAPTER RATING 0.50A 0.75A 1.00A 1.25A 1.50A 1.75A 2.00A RCL VALUE (1%) 0.200 0.133 0.100 0.080 0.067 0.057 0.050 RCL POWER DISSIPATION 0.050W 0.075W 0.100W 0.125W 0.150W 0.175W 0.200W RCL POWER RATING 0.25W 0.25W 0.25W 0.25W 0.25W 0.25W 0.25W
Programming Input Current Limit To set the input current limit ILIM, the minimum wall adapter current rating must be known. To account for the tolerance of the LTC4009 input current sense circuit, 5% should be subtracted from the adapter's minimum rated output. Refer to Figure 6 and program the input current limit function with the following equation. RCL = 100mV ILIM
Figure 7 shows an optional circuit that can influence the parameters of the input current limit in two ways. The first option is to lower the power dissipation of RCL at the expense of accuracy without changing the input current
DCIN D1 INPUT DIODE CLP LTC4009 CLN 1 R2 Q1 IMX1 R1 1% R3 = R1 1%
4009 F07
where ILIM is the desired maximum current draw from the DC (adapter) input, including adjustments for tolerance, if any. Often an AC adapter will include a rated current output margin of at least +10%. This can allow the adapter current limit value to simply be programmed to the actual minimum rated adapter output current. Table 4 shows some common RCL current limit programming values. A lowpass filter formed by RF (5.1k) and CF (0.1F) is required to eliminate switching noise from the LTC4009 PWM and other system components. If input current limiting is not desired, CLN should be shorted to CLP while CLP remains connected to power.
2 CF 0.22F RF 2.49k 1% RCL 1% TO REMAINDER OF SYSTEM Q2 2SC2412
INTVDD 17
Figure 7. Adjusting Input Current Limit
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LTC4009 LTC4009-1/LTC4009-2 APPLICATIONS INFORMATION
limit value. The second is to make the input current limit value programmable. The overall accuracy of this circuit needs to be better than the power source current tolerance or be margined such that the worse-case error remains under the power source limits. The accuracy of the Figure 7 circuit is a function of the INTVDD, VBE, RCL, RF, R1 and R3 tolerances. To improve accuracy, the tolerance of RF should be changed from 5.1k, 5% to a 2.49k 1% resistor. RCL and the programming resistors R1 and R3 should also be 1% tolerance such that the dominant error is INTVDD (3%). Bias resistor R2 can be 5%. When choosing NPN transistors, both need to have good gain (>100) at 10A levels. Low gain NPNs will increase programming errors. Q1 must be a matched NPN pair. Since RF has been reduced in value by half, the capacitor value of CF should double to 0.22F to remain effective at filtering out any noise. If you wish to reduce RCL power dissipation for a given current limit, the programming equation becomes: 5 * 2.49k 100mV - R1 = ILIM the three ground connections shown in Figure 7, combine them into one common connection and use a small-signal NFET (2N7002) to open or close that common connection to circuit ground. When the NFET is off, the circuit is defeated (floating) allowing ILIM to be the maximum value. When the NFET is on, the circuit will become active and ILIM will drop to the lower set value. Monitoring Charge Current The PROG pin voltage can be used to indicate charge current where 1.2085V indicates full programmed current (1C) and zero charge current is approximately equal to RPROG * 11.67A. PROG voltage varies in direct proportion to the charge current between this zero-current (offset) value and 1.2085V. When monitoring the PROG pin voltage, using a buffer amplifier as shown in Figure 8 will minimize charge current errors. The buffer amplifier may be powered from the INTVDD pin or any supply that is always on when the charger is on.
RCL
INTVDD 17 LTC4009 PROG 13 <30nA
If you wish to make the input current limit programmable, the equation becomes: 5 * 2.49k 100mV - R1 ILIM = RCL The equation governing R2 for both applications is based on the value of R1. R3 should always be equal to R1. R2 = 0.875 * R1 In many notebook applications, there are situations where two different ILIM values are needed to allow two different power adapters or power sources to be used. In such cases, start by setting RLIM for the high power ILIM configuration and then use Figure 7 to set the lower ILIM value. To toggle between the two ILIM values, take
Figure 8. PROG Voltage Buffer
C/10 CHRG Indicator The value chosen for RPROG has a strong influence on charge current monitoring and the accuracy of the C/10 charge indicator output (CHRG). The LTC4009 uses the voltage on the PROG pin to determine when charge current has dropped to the C/10 threshold. The nominal threshold of 400mV produces an accurate low charge current indication of C/10 as long as RPROG = 26.7k, independent of all other current programming considerations. However, it may sometimes be necessary to deviate from this value to satisfy other application design goals.
18
+ -
4009 F08
TO SYSTEM MONITOR
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LTC4009 LTC4009-1/LTC4009-2 APPLICATIONS INFORMATION
If RPROG is greater than 26.7k, the actual level at which low charge current is detected will be less than C/10. The highest value of RPROG that can be used while reliably indicating low charge current before reaching final VBAT is 30.1k. RPROG can safely be set to values higher than this, but low current indication will be lost. If RPROG is less than 26.7k, low charge current detection occurs at a level higher than C/10. More importantly, the LTC4009 becomes increasingly sensitive to reverse current. The lowest value of RPROG that can be used without the risk of erroneous boost operation detection at end of charge is 26.1k. Values of RPROG less than this should not be used. See the Operation section for more information about reverse current. The nominal fractional value of IMAX at which C/10 indication occurs is given by: 400mV - (RPROG * 11.67A) IC10 = IMAX 1.2085V - (RPROG * 11.67A) Direct digital monitoring of C/10 indication is possible with an external application circuit like the one shown in Figure 9. The LTC4009 initially indicates C/10 until the PWM has started and the actual charge current can be determined (PROG pin voltage). The 0.1F capacitor from CHRG to GND is used to filter this initial pulse, which is typically less than 2ms when starting toward a final charge current that is actually greater than C/10. If external circuitry is insensitive to, or can ignore, this momentary C/10 indication at start-up, the capacitor can be omitted. By using two different value pull-up resistors, a microprocessor can detect three states from this pin (charging, C/10 and not charging). See Figure 10. When a digital output port (OUT) from the microprocessor drives one of the resistors and a second digital input port polls the network, the charge state can be determined as shown in Table 5.
3.3V
LTC4009 CHRG 8
200k 33k
VDD P OUT IN
4009 F10
Figure 10. Microprocessor Status Interface Table 5. Digital Read Back State (IN, Figure 10)
LTC4009 CHARGER STATE Off C/10 Charge Bulk Charge OUT STATE Hi-Z 1 0 0 1 1 1 0
VLOGIC INTVDD 17 100k LTC4009 CHRG 8 0.1F Q3 2N7002 100k Q1 TP0610T Q2 2N7002 100k 100k C/10 CHRG
4009 F09
Figure 9. Digital C/10 Indicator
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LTC4009 LTC4009-1/LTC4009-2 APPLICATIONS INFORMATION
Input and Output Capacitors In addition to typical input supply bypassing (0.1F) on DCIN, the relatively high ESR of aluminum electrolytic capacitors is helpful for reducing ringing when hot pluging the charger to the AC adapter. Refer to LTC Application Note 88 for more information. The input capacitor between system power (drain of top FET, Figure 1) and GND is required to absorb all input PWM ripple current, therefore it must have adequate ripple current rating. Maximum RMS ripple current is typically one-half of the average battery charge current. Actual capacitance value is not critical, but using the highest possible voltage rating on PWM input capacitors will minimize problems. Consult with the manufacturer before use. The output capacitor shown across the battery and ground must also absorb PWM output ripple current. The general formula for this capacitor current is: V 0.29 * VBAT * 1 - BAT VCLP L1 * fPWM but exercise caution when using tantalum for input or output bulk capacitors. High input surge current can be created when the adapter is hot-plugged to the charger or when a battery is connected to the charger. Solid tantalum capacitors have a known failure mechanism when subjected to very high surge currents. Select tantalum capacitors that have high surge current ratings or have been surge tested. EMI considerations usually make it desirable to minimize ripple current in battery leads. Adding Ferrite beads or inductors can increase battery impedance at the nominal 550KHz switching frequency. Switching ripple current splits between the battery and the output capacitor in inverse relation to capacitor ESR and the battery impedance. If the ESR of the output capacitor is 0.2 and the battery impedance is raised to 4 with a ferrite bead, only 5% of the current ripple will flow to the battery. Inductor Selection Higher switching frequency generally results in lower efficiency because of MOSFET gate charge losses, but it allows smaller inductor and capacitor values to be used. A primary effect of the inductor value L1 is the amplitude of ripple current created. The inductor ripple current IL decreases with higher inductance and PWM operating frequency: V VBAT * 1 - BAT VCLP IL = L1 * fPWM Accepting larger values of IL allows the use of low inductance, but results in higher output voltage ripple and greater core losses. Lower charge currents generally call for larger inductor values.
IRMS =
For example, IRMS = 0.22A with: VBAT = 12.6V VCLP = 19V L1 = 10H fPWM = 550kHz High capacity ceramic capacitors (20F or more) available from a variety of manufacturers can be used for input/output capacitors. Other alternatives include OS-CON and POSCAP capacitors from Sanyo. Low ESR solid tantalum capacitors have high ripple current rating in a relatively small surface mount package,
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LTC4009 LTC4009-1/LTC4009-2 APPLICATIONS INFORMATION
The LTC4009 limits maximum instantaneous peak inductor current during every PWM cycle. To avoid unstable switch waveforms, the ripple current must satisfy: 150mV IL < 2 * - IMAX RSENSE so choose: L1 > 0.125 * VCLP 150mV fPWM * - IMAX RSENSE maximum IL near 0.6 * IMAX with fPWM at 550kHz and VBAT = 0.5 * VCLP (the point of maximum IL), assuming that inductor value could also vary by 25% at IMAX.
Table 6. Minimum Typical Inductor Values VCLP L1 (Typ) IMAX RSENSE
<10V 10V to 20V >20V <10V 10V to 20V >20V 10H 20H 28H 5.1H 10H 14H 1A 1A 1A 2A 2A 2A 100m 100m 100m 50m 50m 50m
RIN
3.01k 3.01k 3.01k 3.01k 3.01k 3.01k
RPROG
26.7k 26.7k 26.7k 26.7k 26.7k 26.7k
A reasonable starting point for setting ripple current is IL = 0.4 * IMAX. The voltage compliance of internal LTC4009 circuits also imposes limits on ripple current. Select RIN (in Figure 1) to avoid average current errors in high ripple designs. The following equation can be used for guidance: RSENSE * IL R * IL RIN SENSE 50A 20A RIN should not be less than 2.37k or more than 6.04k. Values of RIN greater than 3.01k may cause some reduction in programmed current accuracy. Use these equations and guidelines, as represented in Table 6, to help select the correct inductor value. This table was developed to maintain
To guarantee that a chosen inductor is optimized in any given application, use the design equations provided and perform bench evaluation in the target application, particularly at duty cycles below 20% or above 80% where PWM frequency can be much less than the nominal value of 550kHz. TGATE BOOST Supply Use the external components shown in Figure 11 to develop a bootstrapped BOOST supply for the TGATE FET driver. A good set of equations governing selection of the two capacitors is: C1 = 20 * QG , C2 = 20 * C1 4.5V
BOOST 20 LTC4009 INTVDD 17 D1 1N4148 C2 2F C1 0.1F L1 TO RSENSE
SW 18
4009 F11
Figure 11. TGATE Boost Supply
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LTC4009 LTC4009-1/LTC4009-2 APPLICATIONS INFORMATION
where QG is the rated gate charge of the top external NFET with VGS = 4.5V. The maximum average diode current is then given by: ID = QG * 665kHz To improve efficiency by increasing VGS applied to the top FET, substitute a Schottky diode with low reverse leakage for D1. PWM jitter has been observed in some designs operating at higher VIN/VOUT ratios. This jitter does not substantially affect DC charge current accuracy. A series resistor with a value of 5 to 20 can be inserted between the cathode of D1 and the BOOST pin to remove this jitter if present. A resistor case size of 0603 or larger is recommended to lower ESL and achieve the best results. FET Selection Two external power MOSFETs must be selected for use with the charger: an N-channel power switch (top FET) and an N-channel synchronous rectifier (bottom FET). Peak gate-to-source drive levels are internally set to about 5V. Consequently, logic-level FETs must be used. In addition to the fundamental DC current, selection criteria for these MOSFETs also include channel resistance RDS(ON), total gate charge QG, reverse transfer capacitance CRSS, maximum rated drain-source voltage BVDSS and switching characteristics such as td(ON/OFF). Power dissipation for each external FET is given by: PD(TOP) = VBAT * IMAX 2 * (1+ T)RDS(ON) VCLP + k * VCLP 2 * IMAX * CRSS * 665kHz PD(BOT) where is the temperature dependency of RDS(ON), T is the temperature rise above the point specified in the FET data sheet for RDS(ON) and k is a constant inversely related to the internal LTC4009 top gate driver. The term (1 + T) is generally given for a MOSFET in the form of a normalized RDS(ON) curve versus temperature, but of 0.005/C can be used as a suitable approximation for logic-level FETs if other data is not available. CRSS = QGD/dVDS is usually specified in the MOSFET characteristics. The constant k = 2 can be used in estimating top FET dissipation. The LTC4009 is designed to work best with external FET switches with a total gate charge at 5V of 15nC or less. For VCLP < 20V, high charge current efficiency generally improves with larger FETs, while for VCLP > 20V, top gate transition losses increase rapidly to the point that using a topside NFET with higher RDS(ON) but lower CRSS can actually provide higher efficiency. If the charger will be operated with a duty cycle above 85%, overall efficiency is normally improved by using a larger top FET. The synchronous (bottom) FET losses are greatest at high input voltage or during a short circuit, which forces a low side duty cycle of nearly 100%. Increasing the size of this FET lowers its losses but increases power dissipation in the LTC4009. Using asymmetrical FETs will normally achieve cost savings while allowing optimum efficiency. Select FETs with BVDSS that exceeds the maximum VCLP voltage that will occur. Both FETs are subjected to this level of stress during operation. Many logic-level MOSFETs are limited to 30V or less.
(VCLP - VBAT ) * IMAX 2 * (1+ T)RDS(ON) =
VCLP
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LTC4009 LTC4009-1/LTC4009-2 APPLICATIONS INFORMATION
The LTC4009 uses an improved adaptive TGATE and BGATE drive that is insensitive to MOSFET inertial delays, td(ON/OFF), to avoid overlap conduction losses. Switching characteristics from power MOSFET data sheets apply only to a specific test fixture, so there is no substitute for bench evaluation of external FETs in the target application. In general, MOSFETs with lower inertial delays will yield higher efficiency. Diode Selection A Schottky diode in parallel with the bottom FET and/or top FET in an LTC4009 application clamps SW during the non-overlap times between conduction of the top and bottom FET switches. This prevents the body diode of the MOSFETs from forward biasing and storing charge, which could reduce efficiency as much as 1%. One or both diodes can be omitted if the efficiency loss can be tolerated. A 1A Schottky is generally a good size for 3A chargers due to the low duty cycle of the non-overlap times. Larger diodes can actually result in additional efficiency (transition) losses due to larger junction capacitance. Loop Compensation and Soft-Start The three separate PWM control loops of the LTC4009 can be compensated by a single set of components attached between the ITH pin and GND. As shown in the typical LTC4009 application, a 6.04k resistor in series with a capacitor of at least 0.1F provides adequate loop compensation for the majority of applications. The LTC4009 can be soft-started with the compensation capacitor on the ITH pin. At start-up, ITH will quickly rise to about 0.25V, then ramp up at a rate set by the compensation capacitor and the 40A ITH bias current. The full programmed charge current will be reached when ITH reaches approximately 2V. With a 0.1F capacitor, the time to reach full charge current is usually greater than 1.5ms. This capacitor can be increased if longer start-up times are required, but loop bandwidth and dynamic response will be reduced. INTVDD Regulator Output Bypass the INTVDD regulator output to GND with a low ESR X5R or X7R ceramic capacitor with a value of 0.47F or larger. The capacitor used to build the BOOST supply (C2 in Figure 11) can serve as this bypass. Do not draw more than 30mA from this regulator for the host system, governed by IC power dissipation. Calculating IC Power Dissipation The user should ensure that the maximum rated junction temperature is not exceeded under all operating conditions. The thermal resistance of the LTC4009 package (JA) is 37C/W, provided the Exposed Pad is in good thermal contact with the PCB. The actual thermal resistance in the application will depend on forced air cooling and other heat sinking means, especially the amount of copper on the PCB to which the LTC4009 is attached. The following formula may be used to estimate the maximum average power dissipation PD (in watts) of the LTC4009, which is dependent upon the gate charge of the external MOSFETs. This gate charge, which is a function of both gate and drain voltage swings, is determined from specifications or graphs in the manufacturer's data sheet. For the equation below, find the gate charge for each transistor assuming 5V gate swing and a drain voltage swing equal to the maximum VCLP voltage. Maximum LTC4009 power dissipation under normal operating conditions is then given by: PD = DCIN(2.8mA + IDD + 665kHz(QTGATE + QBGATE)) - 5IDD where: IDD = Average external INTVDD load current, if any QTGATE = Gate charge of external top FET in Coulombs QBGATE = Gate charge of external bottom FET in Coulombs
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LTC4009 LTC4009-1/LTC4009-2 APPLICATIONS INFORMATION
PCB Layout Considerations To prevent magnetic and electrical field radiation and high frequency resonant problems, proper layout of the components connected to the LTC4009 is essential. Refer to Figure 12. For maximum efficiency, the switch node rise and fall times should be minimized. The following PCB design priority list will help insure proper topology. Layout the PCB using this specific order. 1. Input capacitors should be placed as close as possible to switching FET supply and ground connections with the shortest copper traces possible. The switching FETs must be on the same layer of copper as the input capacitors. Vias should not be used to make these connections. 2. Place the LTC4009 close to the switching FET gate terminals, keeping the connecting traces short to produce clean drive signals. This rule also applies to IC supply and ground pins that connect to the switching FET source pins. The IC can be placed on the opposite side of the PCB from the switching FETs. 3. Place the inductor input as close as possible to the switching FETs. Minimize the surface area of the switch node. Make the trace width the minimum needed to support the programmed charge current. Use no copper fills or pours. Avoid running the connection on multiple copper layers in parallel. Minimize capacitance from the switch node to any other trace or plane.
SWITCH NODE L1 VIN CIN HIGH FREQUENCY CIRCULATING PATH COUT D1 RSENSE VBAT
4. Place the charge current sense resistor immediately adjacent to the inductor output, and orient it such that current sense traces to the LTC4009 are not long. These feedback traces need to be run together as a single pair with the smallest spacing possible on any given layer on which they are routed. Locate any filter component on these traces next to the LTC4009, and not at the sense resistor location. 5. Place output capacitors adjacent to the sense resisitor output and ground. 6. Output capacitor ground connections must feed into the same copper that connects to the input capacitor ground before connecting back to system ground. 7. Connection of switching ground to system ground, or any internal ground plane, should be single-point. If the system has an internal system ground plane, a good way to do this is to cluster vias into a single star point to make the connection. 8. Route analog ground as a trace tied back to the LTC4009 GND paddle before connecting to any other ground. Avoid using the system ground plane. A useful CAD technique is to make analog ground a separate ground net and use a 0 resistor to connect analog ground to system ground. 9. A good rule of thumb for via count in a given high current path is to use 0.5A per via. Be consistent when applying this rule.
+
BAT ANALOG GROUND
GND SWITCHING GROUND
4009 F12
SYSTEM GROUND
Figure 12. High Speed Switching Path
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24
LTC4009 LTC4009-1/LTC4009-2 APPLICATIONS INFORMATION
10. If possible, place all the parts listed above on the same PCB layer. 11. Copper fills or pours are good for all power connections except as noted above in Rule 3. Copper planes on multiple layers can also be used in parallel. This helps with thermal management and lowers trace inductance, which further improves EMI performance. 12. For best current programming accuracy, provide a Kelvin connection from RSENSE to CSP and CSN. See Figure 13 for an example. 13. It is important to minimize parasitic capacitance on the CSP and CSN pins. The traces connecting these pins to their respective resistors should be as short as possible.
DIRECTION OF CHARGING CURRENT
RSENSE
4009 F13
TO CSP RIN
TO CSN RIN
Figure 13. Kelvin Sensing of Charge Current
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LTC4009 LTC4009-1/LTC4009-2 TYPICAL APPLICATION
12.6V 2 Amp Charger
R7 50m POWER TO SYSTEM C1 0.1F D1 R1 3k R 8 3 R2 22.1k R3 2.43k 5 CHRG DCIN DCDIV CLP CLN BOOST C4 0.1F 2 1 20 R15 0* C5 0.1F D3 D4 C6 2F R9 3.01k R11 50m Q3 L1 10H R8 5.1k C8 10F Q2 D5 OR R14 100k D6 18V ZENER Q4 PFET FDR858P TO POWER SYSTEM LOAD WHEN ADAPTER IS NOT PRESENT, USE SCHOTTKY DIODE D5 OR THE COMBINATION OF R14, D6 AND Q4
FROM ADAPTER 15V AT 2A
D2
TO/FROM MCU
19 TGATE LTC4009 18 SW 7 17 ACP INTVDD 4 16 ICL BGATE 6 12 C2 0.1F R4 6.04k 13 SHDN GND ITH CSP 21 15
CSN
14 11
R10 3.01k
BAT 9 FBDIV PROG VFB
R5 26.7k BULK CHARGE Q1 R6 53.6k
C3 4.7nF
10
R12 294k R13 31.2k
C10 10pF
C9 10F
+
12.6V Li-Ion BATTERY
4009 TA02
D2, D4: MBR230LSFT1 D3:CMDSH-3 Q1: 2N7002 Q2, Q3: Si7212DN OR SiA914DJ OR Si4816BDY (OMIT D4) L1: IHLP-2525CZER100M11 *SEE TGATE BOOST SUPPLY IN APPLICATIONS INFORMATION
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LTC4009 LTC4009-1/LTC4009-2 PACKAGE DESCRIPTION
UF Package 20-Lead Plastic QFN (4mm x 4mm)
(Reference LTC DWG # 05-08-1710 Rev A)
0.70 0.05 4.50 0.05 3.10 0.05 2.00 REF 2.45 0.05 2.45 0.05
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 0.75 0.05 R = 0.05 TYP BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 19 20 0.40 0.10 1 2.00 REF 2.45 0.10 2 PIN 1 NOTCH R = 0.20 TYP OR 0.35 x 45 CHAMFER
PIN 1 TOP MARK (NOTE 6)
4.00 0.10
2.45 0.10
(UF20) QFN 01-07 REV A
0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-1)--TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 0.05 0.50 BSC
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC4009 LTC4009-1/LTC4009-2 RELATED PARTS
PART NUMBER LTC1760 LTC1769 LTC1960 LTC4006 LTC4007/LTC4007-1 LTC4008/LTC4008-1 DESCRIPTION Smart Battery System Manager 2A Switching Battery Charger Dual Battery Charger/Selector with SPI Small, High Efficiency, Fixed Voltage, Lithium-Ion Battery Chargers with Termination High Efficiency, Programmable Voltage, Lithium-Ion Battery Charger with Termination COMMENTS Autonomous Power Management and Battery Charging for Two Smart Batteries, SMBus Rev 1.1 Compliant Constant-Current/Constant-Voltage Switching Regulator, Input Current Limiting Maximizes Charge Current 11-Bit V-DAC, 0.8% Voltage Accuracy, 10-Bit I-DAC, 5% Current Accuracy Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current Limit and Thermistor Sensor, 16-Pin SSOP Package Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current Limit, Thermistor Sensor and Indicator Outputs
High Efficiency, Programmable Voltage/Current Battery Constant-Current/Constant-Voltage Switching Regulator, Resistor Chargers Voltage/Current Programming, Thermistor Sensor and Indicator Outputs, AC Adapter Current Limit (Omitted on 4008-1) High Efficiency Standalone Nickel Battery Charger High Efficiency Standalone Nickel Battery Charger High Efficiency, Multichemistry Battery Chargers with PowerPath Control Standalone Linear NiMH/NiCd Fast Charger Smart Battery Charger Controller Battery Backup Manager Complete NiMH/NiCd Charger in a Small 16-Lead Package, ConstantCurrent Switching Regulator Complete NiMH/NiCd Charger in a Small 20-Lead Package, ConstantCurrent Switching Regulator, PowerPathTM Control and Indicators Constant-Current/Constant-Voltage Switching Regulator in a 20-Lead QFN Package, AC Adapter Current Limit, PFET Input Ideal Diode Control, Indicator Outputs Complete NiMH/NiCd Charger in a Small 16-Pin Package, No Sense Resistor or Blocking Diode Required Level 2 Charger Operates With or Without MCU Host, SMBus Rev 1.1 Compliant Multi-Chemistry and Smart Battery Charge and Discharge Manager. Four Operating Modes: Battery Backup, Battery Charge, Battery Calibration, Shutdown. 5mm x 7mm QFN-38 Package High Side Sense of Charge Quantity and Polarity in a 10-Pin MSOP No External MOSFET, Automatic Switching Between DC Sources, 140m On-Resistance in ThinSOTTM package Very Low Loss Replacement for Power Supply ORing Diodes Using Minimal External Complements, Operates Up to 28V (36V for HV) Low Loss Replacement for ORing Diodes, 100m On-Resistance Low Loss Replacement for ORing Diodes, Operates Up to 36V Low Loss Replacement for ORing Diodes, Operates Up to 36V, Drives Large PFETs, Programmable, Autonomous Switching
LTC4010 LTC4011 LTC4012/LTC4012-1 LTC4012-2 LTC4060 LTC4100 LTC4110
LTC4150 LTC4411 LTC4412/LTC4412HV LTC4413 LTC4414 LTC4416
Coulomb Counter/Battery Gas Gauge 2.6A Low Loss Idea Diode Low Loss PowerPath Controllers Dual 2.6A, 2.5V to 5.5V Ideal Diodes 36V, Low Loss PowerPath Controller for Large PFETs Dual Low Loss PowerPath Controllers
PowerPath and ThinSOT are trademarks of Linear Technology Corporation.
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28 Linear Technology Corporation
(408) 432-1900
LT 0109 REV B * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
FAX: (408) 434-0507 www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2008

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